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NCP5392Q 2/3/4-Phase Controller for CPU Applications
The NCP5392Q provides up to a four-phase buck solution which combines differential voltage sensing, differential phase current sensing, and adaptive voltage positioning to provide accurately regulated power for Intel processors. Dual-edge pulse-width modulation (PWM) combined with inductor current sensing reduces system cost by providing the fastest initial response to dynamic load events. Dual-edge multiphase modulation reduces the total bulk and ceramic output capacitance required to meet transient regulation specifications. A high performance operational error amplifier is provided to simplify compensation of the system. Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between closed-loop transient response and Dynamic VID performance. In addition, NCP5392Q provides an automatic power saving feature (Auto-PSI). When Auto-PSI function is enabled, NCP5392Q will automatically detect the VID transitions and direct the Vcore regulator in or out of low power states. As a result, the best efficiency scheme is always chosen.
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1 40 40 PIN QFN, 6x6 MN SUFFIX CASE 488AR
NCP5392Q AWLYYWWG
NCP5392Q = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package *Pin 41 is the thermal pad on the bottom of the device.
* * * * * * * * * * * * * * * * * * * * * *
Meets Intel's VR11.1 Specifications Dual-edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifier Internal Soft Start Dynamic Reference Injection (Patent #US07057381) DAC Range from 0.375 V to 1.6 V DAC Feed Forward Function (Patent Pending) 0.5% DAC Voltage Accuracy from 1.0 V to 1.6 V True Differential Remote Voltage Sensing Amplifier Phase-to-Phase Current Balancing "Lossless" Differential Inductor Current Sensing Differential Current Sense Amplifiers for each Phase Adaptive Voltage Positioning (AVP) Oscillator Frequency Range of 100 kHz - 1 MHz Latched Over Voltage Protection (OVP) Guaranteed Startup into Pre-Charged Loads Threshold Sensitive Enable Pin for VTT Sensing Power Good Output with Internal Delays Thermally Compensated Current Monitoring Automatic Power Saving (AUTO PSI Mode) Compatible to PSI Power Saving Requirements This is a Pb-Free Device
ORDERING INFORMATION
Device NCP5392QMNR2G* Package Shipping
QFN-40 2500/T ape & Reel (Pb-Free)
*Temperature Range: 0C to 85C For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Applications
* Desktop Processors
(c) Semiconductor Components Industries, LLC, 2009
June, 2009 - Rev. 0
1
Publication Order Number: NCP5392Q/D
NCP5392Q
PIN CONNECTIONS
40 39 38 37 36 35 34 33 32 G3 31 G2
NC
APSI_EN
1 2 3 4 5 6 7 8 9 10
12VMON
VR_RDY
DAC
PSI
VCC
G4
EN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
G1 DRVON CS4 CS4N
30 29 28 27 26 25 24 23 22 21
NCP5392Q 2/3/4-Phase Buck Controller (QFN40)
CS3 CS3N CS2 CS2N CS1
11
12
13
14
15
16
17
18
19
Figure 1. NCP5392Q QFN40 Pin Connections (Top View)
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20
CSSUM
COMP
VDRP
ROSC IMON VSN VSP ILIM
DIFFOUT
VDFB
CS1N
VFB
NCP5392Q
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 DAC
Flexible DAC Overvoltage Protection - +
VSN VSP
- + Diff Amp
+ - G1
DIFFOUT + VFB COMP VDRP VDFB CSSUM CS1P CS1N CS2P CS2N CS3P CS3N CS4P CS4N + - + - + - + - + - Droop Amp -2/3 + + Gain = 6 + Gain = 6 + Gain = 6 + Gain = 6 + + - G4 + - G3 1.3 V Error Amp + - G2
+ -
Oscillator ROSC + ILIM EN VCC 4.25 V + + - UVLO - ILimit Control, Fault Logic and Monitor Circuits
IMON
DRVON PSI APSI_EN 12VMON VR_RDY
GND (FLAG)
Figure 2. NCP5392Q Block Diagram
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NCP5392Q
12V_FILTER +5V 12V_FILTER VTT D1 C4 VTT C1 34 12VMON 2 3 4 5 6 7 8 9 1 39 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 EN VR_RDY 35 VCC U2 37 PSI 38 APSI_EN 40 NC IMON 12 G1 CS1P CS1N G2 CS2P 14 RFB CFB1 CF CS2N VSN NCP5392Q G3 CS3P CS3N RFB1 RF 15 16 17 CH RDRP RNOR 18 19 R6 20 36 DIFFOUT COMP VFB VDRP VDFB CSSUM DAC ROSC GND ILIM DRVON 29 G4 CS4P CS4N 30 22 21 31 24 23 32 26 25 33 28 27 VCC BST DRH NCP5359 SW OD DRL IN PGND 12V_FILTER 12V_FILTER IMON PSI APSI_EN BST VCC DRH NCP5359 SW OD DRL IN PGND C2 CS1 Q2 R2 C3 Q1 L1 12V_FILTER
RS1
13 VSP
12V_FILTER
12V_FILTER +
CDFB RISO1 RT2 RISO2
CDNI
41 RDNP
11
10 VCC RLIM1
BST DRH NCP5359 SW OD DRL RLIM2 IN PGND
12V_FILTER
12V_FILTER
BST VCC DRH NCP5359 SW OD IN DRL PGND
VCCP VSSN
Figure 3. Application Schematic for Four Phases
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CPU GND
NCP5392Q
12V_FILTER +5V 12V_FILTER VTT D1 C4 VTT U2 PSI APSI_EN NC 37 38 40 IMON PSI APSI_EN IN C1 BST VCC DRH NCP5359 SW OD DRL PGND C2 CS1 Q2 R2 C3 Q1 L1 12V_FILTER
34 12VMON 2 3 4 5 6 7 8 9 1 39 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 EN
35 VCC
RS1
IMON 12 G1 CS1P CS1N G2 CS2P 30 22 21 31 24 23 32 26 25 33 28 27
12V_FILTER
12V_FILTER
VR_RDY
14 RFB CFB1 CF
CS2N G3 CS3P CS3N
VSN NCP5392Q 13 VSP
BST VCC DRH NCP5359 SW OD DRL IN PGND
RFB1 RF
15 16 17
DIFFOUT COMP VFB VDRP VDFB CSSUM DAC
G4 CS4P CS4N
CH RDRP RNOR R6
18 19 20 36
DRVON
29
12V_FILTER
12V_FILTER +
CDFB RISO1 RT2 RISO2
CDNI
ROSC
GND
ILIM
41 RDNP
11
10 VCC RLIM1
BST DRH NCP5359 SW OD DRL RLIM2 IN PGND
VCCP VSSN
Figure 4. Application Schematic for Three Phases
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CPU GND
NCP5392Q
12V_FILTER +5V 12V_FILTER VTT D1 C4 VTT C1 BST VCC DRH NCP5359 SW OD DRL IN PGND C2 CS1 Q2 R2 C3 Q1 L1 12V_FILTER
34 12VMON 2 3 4 5 6 7 8 9 1 39 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 EN
35 VCC PSI APSI_EN NC
U2 37 38 40 IMON
RNTC1 PSI APSI_EN
RS1
IMON 12 G1 CS1P CS1N G2 CS2P 30 22 21 31 24 23 32 26 25 33 28 27
VR_RDY
14 RFB CFB1 CF
CS2N VSN NCP5392Q G3
13 VSP
CS3P CS3N
RFB1 RF
15 16 17
DIFFOUT COMP VFB VDRP VDFB CSSUM DAC
G4 CS4P CS4N
CH RDRP RNOR R6
18 19 20 36
DRVON
29
12V_FILTER
12V_FILTER +
CDFB RISO1 RT2 RISO2
CDNI
ROSC
GND
ILIM
41 RDNP
11
10 VCC RLIM1
BST DRH NCP5359 SW OD DRL RLIM2 IN PGND
VCCP VSSN
Figure 5. Application Schematic for Two Phases
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CPU GND
NCP5392Q
PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol EN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 ROSC ILIM Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input A resistance from this pin to ground programs the oscillator frequency according to fSW. This pin supplies a trimmed output voltage of 2 V. Overcurrent shutdown threshold setting. Connect this pin to the ROSC pin via a resistor divider as shown in the Application Schematics. To disable the overcurrent feature, connect this pin directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin; do not connect this pin to any externally generated voltages. 0 mV to 900 mV analog signal proportional to the output load current. VSN referenced Non-inverting input to the internal differential remote sense amplifier Inverting input to the internal differential remote sense amplifier Output of the differential remote sense amplifier Output of the error amplifier Compensation Amplifier Voltage feedback Voltage output signal proportional to current used for current limit and output voltage droop Droop Amplifier Voltage Feedback Inverted Sum of the Differential Current Sense inputs. Av=CSSUM/CSx = -4 Inverting input to current sense amplifier #1 Non-inverting input to current sense amplifier #1 Inverting input to current sense amplifier #2 Non-inverting input to current sense amplifier #2 Inverting input to current sense amplifier #3 Non-inverting input to current sense amplifier #3 Inverting input to current sense amplifier #4 Non-inverting input to current sense amplifier #4 Bidirectional Gate Drive Enable PWM output pulse to gate driver. 3-level output: Low = LSFET Enabled, Mid = Diode Emulation Enabled, High = HSFET Enabled PWM output pulse to gate driver. 3-level output (see G1) PWM output pulse to gate driver. 3-level output (see G1) PWM output pulse to gate driver. 3-level output (see G1) Monitor a 12 V input through a resistor divider. Power for the internal control circuits. DAC Feed Forward Output Power Saving Control. Low = power saving operation, High = normal operation. PSI signal has higher priority over APSI_EN signal. APSI_EN High: Enable AUTO PSI function. When PSI = low, system will be forced into PSI mode, unconditionally. When PSI = high, APSI_EN will determine if the system needs to be in AUTO PSI mode. Once in AUTO PSI mode, system switches on/off PSI functions automatically based on VID change status. Open collector output. High indicates that the output is regulating Not Connected Power supply return (QFN Flag) Description Threshold sensitive input. High = startup, Low = shutdown.
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
IMON VSP VSN DIFFOUT COMP VFB VDRP VDFB CSSUM CS1N CS1 CS2N CS2 CS3N CS3 CS4N CS4 DRVON G1 G2 G3 G4 12VMON VCC DAC PSI APSI_EN
39 40 FLAG
VR_RDY NC GND
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NCP5392Q
PIN CONNECTIONS VS. PHASE COUNT
Number of Phases 4 3 2 G4 Phase 4 Out Tie to GND Tie to GND G3 Phase 3 Out Phase 3 Out Phase 2 Out G2 Phase 2 Out Phase 2 Out Tie to GND G1 Phase 1 Out Phase 1 Out Phase 1 Out CS4-CS4N Phase 4 CS input Tie to CSN pin used Tie to CSN pin used CS3-CS3N Phase 3 CS input Phase 3 CS input Phase 2 CS input CS2-CS2N Phase 2 CS input Phase 2 CS input Tie to CSN pin used CS1-CS1N Phase 1 CS input Phase 1 CS input Phase 1 CS input
MAXIMUM RATINGS
ELECTRICAL INFORMATION Pin Symbol COMP VDRP V- DIFFOUT VR_RDY VCC ROSC IMON Output All Other Pins VMAX 5.5 V 5.5 V GND + 300 mV 5.5 V 5.5 V 7.0 V 5.5 V 1.1 V 5.5 V -0.3 V VMIN -0.3 V -0.3 V GND - 300 mV -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE 10 mA 5 mA 1 mA 20 mA N/A N/A 1 mA ISINK 10 mA 5 mA 1 mA 20 mA 20 mA 10 mA N/A
*All signals referenced to AGND unless otherwise noted. THERMAL INFORMATION Rating Thermal Characteristic, QFN Package (Note 1) Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level, QFN Package Symbol RqJA TJ TA TSTG MSL Value 34 0 to 125 0 to +85 -55 to +150 1 Unit C/W C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM. 2. JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM.
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NCP5392Q
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter ERROR AMPLIFIER Input Bias Current (Note 3) Noninverting Voltage Range (Note 3) Input Offset Voltage (Note 3) Open Loop DC Gain Open Loop Unity Gain Bandwidth Open Loop Phase Margin Slew Rate V+ = V- = 1.1 V CL = 60 pF to GND, RL = 10 KW to GND CL = 60 pF to GND, RL = 10 KW to GND CL = 60 pF to GND, RL = 10 KW to GND DVin = 100 mV, G = - 10 V/V, DVout = 1.5 V - 2.5 V, CL = 60 pF to GND, DC Load = 125 mA to GND ISOURCE = 2.0 mA ISINK = 0.2 mA Vout = 3.5 V Vout = 1.0 V VSN Voltage = 0 V DRVON = Low DRVON = High DRVON = Low DRVON = High -0.3 CL = 80 pF to GND, RL = 10 KW to GND VS+ to VS- = 0.5 to 1.6 V ISOURCE = 2 mA ISINK = 2 mA Vout = 3 V Vout = 0.5 V - 0.98 3.0 - 2.0 2.0 - -200 0 -1.0 - - - - 1.3 - 100 10 80 5 - - - 200 3 1.0 nA V mV dB MHz V/ms Test Conditions Min Typ Max Unit
Maximum Output Voltage Minimum Output Voltage Output source current (Note 3) Output sink current (Note 3) DIFFERENTIAL SUMMING AMPLIFIER VSN Input Bias Current VSP Input Resistance VSP Input Bias Voltage Input Voltage Range (Note 3) -3 dB Bandwidth Closed Loop DC Gain VS to Diffout Maximum Output Voltage Minimum Output Voltage Output source current (Note 3) Output sink current (Note 3) INTERNAL OFFSET VOLTAGE Offset Voltage to the (+) Pin of the Error Amp and the VDRP pin VDROOP AMPLIFIER Input Bias Current (Note 3) Non-inverting Voltage Range (Note 3) Input Offset Voltage (Note 3) Open Loop DC Gain Open Loop Unity Gain Bandwidth Slew Rate Maximum Output Voltage Minimum Output Voltage Output source current (Note 3) Output sink current (Note 3)
3.5 - 2 2
- - - - 30 1.5 17 0.09 0.66 - 10 1.0 - - - - 1.30
- 50 - -
V mV mA mA mA kW V
3.0 - 1.025 - 0.5 - - -
V MHz V/V V V mA mA V
-200 0 V+ = V- = 1.1 V CL = 20 pF to GND including ESD, RL = 1 kW to GND CL = 20 pF to GND including ESD, RL = 1 kW to GND CL = 20 pF to GND including ESD, RL = 1 kW to GND ISOURCE = 4.0 mA ISINK = 1.0 mA Vout = 3.0 V Vout = 1.0 V -4.0 - - - 3 - 4 1 1.3 - 100 10 5 - - - -
200 3 4.0
nA V mV dB
- - - 1 - -
MHz V/ms V V mA mA
3. Guaranteed by design, not tested in production.
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NCP5392Q
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter CSSUM AMPLIFIER Current Sense Input to CSSUM Gain Current Sense Input to CSSUM -3 dB Bandwidth Current Sense Input to CSSUM Output Slew Rate Current Summing Amp Output Offset Voltage Maximum CSSUM Output Voltage Minimum CSSUM Output Voltage Output source current (Note 3) Output sink current (Note 3) PSI (Power Saving Control, Active Low) Enable High Input Leakage Current Upper Threshold Lower Threshold Hysteresis Enable High Input Leakage Current Upper Threshold Lower Threshold Hysteresis DRVON Output High Voltage Sourcing Current for Output High Output Low Voltage Sinking Current for Output Low Delay Time Rise Time Fall Time Internal Pulldown Resistance VCC Voltage when DRVON Output Valid CURRENT SENSE AMPLIFIERS Input Bias Current (Note 3) Common Mode Input Voltage Range (Note 3) Differential Mode Input Voltage Range (Note 3) Input Offset Voltage Current Sense Input to PWM Gain (Note 3) Current Sharing Offset CS1 to CSx CSx = CSxN = 1.1 V, 0 V < CSx - CSxN < 0.1 V, All VID codes CSx = CSxN = 1.4 V - -0.3 -120 -1.0 5.7 -2.5 0 - - - 6.0 - - 2.0 120 1.0 6.3 2.5 nA V mV mV V/V mV Propagation Delay from EN Low to DRVON CL (PCB) = 20 pF, DVo = 10% to 90% CL (PCB) = 20 pF, DVo = 10% to 90% Sourcing 500 mA VCC = 5 V Sinking 500 mA 3.0 - - 2.5 - - - 35 - - 2.5 - - 10 130 10 70 - - 4.0 0.7 - - - - 140 2.0 V mA V mA ns ns ns kW V External 1 K Pullup to 3.3 V VUPPER VLOWER VUPPER - VLOWER External 1k Pullup to 3.3 V VUPPER VLOWER VUPPER - VLOWER - - 450 - - - 450 - - 650 550 100 - 650 550 100 1.0 770 - - 1.0 770 - - mA mV mV mV mA mV mV mV -60 mV < CS < 60 mV CL = 10 pF to GND, RL = 10 kW to GND DVin = 25 mV, CL = 10 pF to GND, Load = 1 k to 1.3 V CSx - CSNx = 0, CSx = 1.1 V CSx - CSxN = -0.15 V (All Phases) ISOURCE = 1 mA CSx - CSxN = 0.066 V (All Phases) ISINK = 1 mA Vout = 3.0 V Vout = 0.3 V -4.00 - - -15 3.0 - 1 1 -3.88 4 4 - - - - - -3.76 - - +15 - 0.3 - - V/V MHz V/s mV V V mA mA Test Conditions Min Typ Max Unit
APSI_EN (AUTO PSI Function Enable, Active High)
3. Guaranteed by design, not tested in production.
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NCP5392Q
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter IMON VDRP to IMON Gain VDRP to IMON -3 dB Bandwidth Output Referred Offset Voltage Minimum Output Voltage Output source current (Note 3) Output sink current (Note 3) Maximum Clamp Voltage OSCILLATOR Switching Frequency Range (Note 3) Switching Frequency Accuracy 2- or 4-Phase ROSC = 49.9 kW ROSC = 24.9 kW ROSC = 10 kW Switching Frequency Accuracy 3-Phase ROSC = 49.9 kW ROSC = 24.9 kW ROSC = 10 kW ROSC Output Voltage MODULATORS (PWM Comparators) Minimum Pulse Width Propagation Delay 0% Duty Cycle 100% Duty Cycle PWM Ramp Duty Cycle Matching PWM Phase Angle Error (Note 3) VR_RDY (POWER GOOD) OUTPUT VR_RDY Output Saturation Voltage VR_RDY Rise Time (Note 3) IPGD = 10 mA, External Pullup of 1 kW to 1.25 V, CTOT = 45 pF, DVo = 10% to 90% VR_RDY Pulled up to 5 V via 2 kW, tR(VCC) 3 x tR(5V) 100 ms tR(VCC) 20 ms VR_RDY = 5.5 V via 1 K VCore Increasing, DAC = 1.3 V - - - 100 0.4 150 V ns FSW = 800 KHz 20 mV of Overdrive COMP Voltage when the PWM Outputs Remain LO COMP Voltage when the PWM Outputs Remain HI Between Any Two Phases Between Adjacent Phases - - - - - 15 30 10 1.3 2.3 90 - - - - - - 15 ns ns V V % 100 200 374 800 191 354 755 1.95 - - - - - - - 2.01 1000 224 414 978 234 434 1000 2.065 V kHz kHz kHz 1.325 V< VDRP < 1.8 V CL = 30 pF to GND, RL = 100 kW to GND VDRP = 1.6 V, ISOURCE = 0 mA VDRP = 1.2 V, ISINK = 100 mA Vout = 1 V Vout = 0.3 V VDRP Voltage = 2 V, RLOAD = 100 k 1.98 - 81 - 300 300 - 2 4 90 - - - - 99 0.11 - - 1.15 2.02 V/V MHz mV V mA mA V Test Conditions Min Typ Max Unit
VR_RDY Output Voltage at Powerup (Note 3) VR_RDY High - Output Leakage Current (Note 3) VR_RDY Upper Threshold Voltage
-
-
1.0
V
- -
- 310
0.2 270
mA mV Below DAC mV Below DAC
VR_RDY Lower Threshold Voltage
VCore Decreasing DAC = 1.3 V VCore Increasing VCore Decreasing Sourcing 500 mA
410
370
VR_RDY Rising Delay VR_RDY Falling Delay PWM OUTPUTS Output High Voltage Mid Output Voltage
- - 3.0 1.4
500 5 - 1.5
- - - 1.6
ms ms V V
3. Guaranteed by design, not tested in production.
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NCP5392Q
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter PWM OUTPUTS Output Low Voltage Delay + Fall Time (Note 3) Delay + Rise Time (Note 3) Output Impedance - HI or LO State 2/3/4-PhASE DETECTION Gate Pin Source Current Gate Pin Threshold Voltage Phase Detect Timer DIGITAL SOFT-START Soft-Start Ramp Time VR11 Vboot time VID INPUT VID Upper Threshold VID Lower Threshold VID Hysteresis VR11 Input Bias Current (Note 3) Delay before Latching VID Change (VID De-Skewing) (Note 3) VID7 Valid Range ENABLE INPUT Enable High Input Leakage Current (Note 3) VR11 Rising Threshold VR11 Falling Threshold VR11 Total Hysteresis Enable Delay Time Rising- Falling Threshold Measure Time from Enable Transitioning HI to when Output Begins Between VDRP - VDFB = 450 mV and VDRP - VDFB = 650 mV Between VDRP - VDFB = 450 mV and VDRP - VDFB = 650 mV Between VDRP - VDFB = 450 mV and VDRP - VDFB = 650 mV Between VDRP - VDFB = 450 mV and VDRP - VDFB = 650 mV VDRP - VDFB = 520 mV Pullup to 1.3 V - - 450 - 2.5 - 650 550 100 200 770 - - 5.0 nA mV mV mV ms Measured from the edge of the 1st VID change 200 - VUPPER VLOWER VUPPER - VLOWER - 450 - 650 550 100 770 - - 200 300 3.33 mV mV mV nA ns V DAC = 0 to DAC = 1.1 V 1.0 400 - 500 1.5 600 ms ms 60 210 15 80 240 20 150 265 27 mA mV ms Sinking 500 mA CL (PCB) = 50 pF, DVo = VCC to GND CL (PCB) = 50 pF, DVo = GND to VCC Resistance to VCC (HI) or GND (LO) - - - - - 10 10 75 0.7 15 15 - V ns ns W Test Conditions Min Typ Max Unit
CURRENT LIMIT ILIM to VDRP Gain ILIM to VDRP Gain in PSI 4 phase ILIM to VDRP Gain in PSI 3 phase ILIM to VDRP Gain in PSI 2 phase ILIM Offset Delay OVERVOLTAGE PROTECTION VR11 Overvoltage Threshold VR11 PSI Overvoltage Threshold (Note 3) Delay 3. Guaranteed by design, not tested in production. DAC +150 (1.6 V DAC) +150 100 DAC +185 DAC +200 (1.6 V DAC) +200 mV mV ns 0.95 - - - -50 - 1 0.25 0.33 0.5 0 100 1.05 - - - 50 - V/V V/V V/V V/V mV ns
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NCP5392Q
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter UNDERVOLTAGE PROTECTION VCC UVLO Start Threshold VCC UVLO Stop Threshold VCC UVLO Hysteresis 12VMON UVLO 12VMON (High Threshold) 12VMON (Low Threshold) DAC (FEED FORWARD FUNCTION) Output Source Current Output Sink Current Max Output Voltage (Note 3) Min Output Voltage (Note 3) VRM 11 DAC Positive DAC Slew Rate System Voltage Accuracy (DAC Value has a 19 mV Offset Over the Output Value) VCC VCC Operating Current EN Low, No PWM - 15 30 mA 3. Guaranteed by design, not tested in production. 1.0 V < DAC < 1.6 V 0.8 V < DAC < 1.0 V 0.5 V < DAC < 0.8 V 11 - - - - - - - 16.5 0.5 5 8 mV/ms % mV mV VOUT = 3 V VOUT = 0.3 V Isource = 2 mA Isink = 2 mA 0.25 1.5 3 0.5 mA mA V V VCC Valid VCC Valid 0.73 0.64 0.77 0.68 0.82 0.73 V V 4 3.8 4.25 4.05 200 4.5 4.3 V V mV Test Conditions Min Typ Max Unit
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NCP5392Q
Table 1. VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 Voltage (V) HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
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NCP5392Q
Table 1. VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 100 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage (V) 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 HEX 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
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NCP5392Q
Table 1. VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage (V) 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 HEX 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
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NCP5392Q
Table 1. VRM11 VID Codes
VID7 800 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 100 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 Voltage (V) 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF HEX 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 FE FF
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NCP5392Q
FUNCTIONAL DESCRIPTION
General High Performance Voltage Error Amplifier
The NCP5392Q provides up to four-phase buck solution which combines differential voltage sensing, differential phase current sensing, and adaptive voltage positioning to provide accurately regulated power necessary for Intel VR11.1 CPU power system. NCP5392Q has been designed to work with the NCP5359 driver.
AUTO-PSI Function
The error amplifier is designed to provide high slew rate and bandwidth. Although not required when operating as the controller of a voltage regulator, a capacitor from COMP to VFB is required for stable unity gain test configurations.
Gate Driver Outputs and 2/3/4 Phase Operation
NCP5392Q makes energy saving possible without receiving PSI signal from the CPU by wisely introducing Auto-PSI feature. The device will monitor VID lines for transition into/out-of Low Power States. When the VID drops (An indication of entering power saving state), the Auot-PSI logic will detect the transition and enable PSI mode. On the other hand, when the VID rises (exiting power saving mode), the Auto-PSI logic detects the transition and exit PSI mode automatically. Auto-PSI uses the dynamic VID(DVID) transitions of VR11.0 and VR11.1 to shed phases. The phase shedding improves the efficiency of the Vcore regulator eventually. In PSI mode, the total current limit is reduced by the ratio of the phase count left after phase shedding. Auto-PSI function can be activated and deactivated by toggling APSI_EN (PIN38), but with lower priority compared to PSI signal. When PSI (PIN37) is pulled to low, the system will be forced into PSI mode unconditionally, and APSI_EN signal will be shielded. NCP5392Q can be operated up to four phases. It operates at one phase mode when the system enter PSI mode automatically (for example, VID down from 1.2 V to 1.1 V).
Remote Output Sensing Amplifier(RSA)
The part can be configured to run in 2-, 3-, or 4-phase mode. In 2-phase mode, phases 1 and 3 should be used to drive the external gate drivers as shown in the 2-phase Applications Schematic, G2 and G4 must be grounded. In 3-phase mode, gate output G4 must be grounded as shown in the 3-phase Applications Schematic. In 4-phase mode all 4 gate outputs are used as shown in the 4-phase Applications Schematic. The Current Sense inputs of unused channels should be connected to VCCP shown in the Application Schematics. Please refer to table "PIN CONNECTIONS vs. PHASE COUNTS" for details.
Differential Current Sense Amplifiers and Summing Amplifier
A true differential amplifier allows the NCP5392Q to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VSP, and the Vcore ground reference point to VSN. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between Vcore and Vcore ground reference points. The RSA also subtracts the DAC (minus VID offset) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage as the floating ground to allow both positive and negative error voltages.
Precision Programmable DAC
Four differential amplifiers are provided to sense the output current of each phase. The inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1, G2, G3, or G4). If a phase is unused, the differential inputs to that phase's current sense amplifier must be shorted together and connected to the output as shown in the 2- and 3-phase Application Schematics. The current signals sensed from inductor DCR are fed into a summing amplifier to have a summed-up output (CSSUM). Signal of CSSUM combines information of total current of all phases in operation. The outputs of current sense amplifiers control three functions. First, the summing current signal (CCSUM) of all phases will go through DROOP amplifier and join the voltage feedback loop for output voltage positioning. Second, the output signal from DROOP amplifier also goes to ILIM amplifier to monitor the output current limit. Finally, the individual phase current contributes to the current balance of all phases by offsetting their ramp signals of PWM comparators.
Thermal Compensation Amplifier with VDRP and VDFB Pins
A precision programmable DAC is provided and system trimmed. This DAC has 0.5% accuracy over the entire operating temperature range of the part. The DAC can be programmed to support either Intel VR11 VID code specifications.
Thermal compensation amplifier is an internal amplifier in the path of droop current feedback for additional adjustment of the gain of summing current and temperature compensation. The way thermal compensation is implemented separately ensures minimum interference to the voltage loop compensation network.
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NCP5392Q
Oscillator and Triangle Wave Generator
A programmable precision oscillator is provided. The oscillator 's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz per phase to 1.0 MHz per phase. The oscillator generates up to 4 symmetrical triangle waveforms with amplitude between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2-, 3- and 4-phase operation the PWM outputs are separated by 180, 120, and 90 angular degrees, respectively.
PWM Comparators with Hysteresis
divider. During power-up, the 12VMON is monitored and the PWM outputs and soft-start circuit are disabled until the voltage exceeds the threshold of its UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering.
Overcurrent Shutdown
Four PWM comparators receive an error signal at their noninverting input. Each comparator receives one of the triangle waves at its inverting output. The output of each comparator generates the PWM outputs G1, G2, G3, and G4. During steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by Vout/Vin. During a transient event, both high and low comparator output transitions shift phase to the points where the error signal intersects the down and up ramp of the triangle wave. PROTECTION FEATURES
Power Saving Mode
A programmable overcurrent function is incorporated within the IC. A comparator and latch make up this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels - effectively disabling overcurrent shutdown. The comparator noninverting input is the summed current information from the VDRP minus offset voltage. The overcurrent latch is set when the current information exceeds the voltage at the ILIM pin. The outputs are pulled low, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high.
Output Overvoltage and Undervoltage Protection and Power Good Monitor
Upon receiving PSI low command, or VID down with Auto-PSI enabled, the NCP5392Q enters power saving mode with only single phase running. The device operates in power saving mode to maintain a high power efficiency and good transient performance.
Undervoltage Lockout
An output voltage monitor is incorporated. During normal operation, if the output voltage is 180 mV (typical) over the DAC voltage, the VR_RDY goes low, the DRVON signal remains high, the PWM outputs are set low. The outputs will remain disabled until the VCC voltage is removed and reapplied. During normal operation, if the output voltage falls more than 350 mV below the DAC setting, the VR_RDY pin will be set low until the output voltage rises.
Soft-Start
An undervoltage lockout (UVLO) senses the VCC input. During power-up, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering.
12VMON UVLO and VIN Information
12V UVLO senses the 12V power supply by connecting it to the 12VMON pin through an appropriate resistor
The VR11 mode ramps Vcore to 1.1 V boot voltage at a fixed rate of 0.8 mV/mS, pauses at 1.1 V for around 500 mS, reads the VID pins to determine the DAC setting. Then ramps Vcore to the final DAC setting at the Dynamic VID slew rate of up to 12.5 mV/mS. Typical VR11 soft-start sequences are shown in the following graphs (Figure 9 and 10).
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NCP5392Q
APPLICATION INFORMATION The NCP5392Q demo board for the NCP5392Q is available by request. It is configured as a four phase solution with decoupling designed to provide a 1 mW load line under a 100 A step load.
Startup Procedure
the lowest VID selection, then enable the test. See Figures 7 and 8.
Start by installing the test tool software. It is best to power the test tool from a separate ATX power supply. The test tool should be set to a valid VID code of 0.5 V or above in order for the controller to start. Consult the VTT help manual for more detailed instruction.
Step Load Testing
The VTT tool is used to generate the di/dt step load. Select the dynamic loading option in the VTT test tool software. Set the desired step load size, frequency, duty, and slew rate. See Figure 6.
Figure 7. 1.6 V to 0.5 V Dynamic VID response
Figure 6. Typical Load Step Response (full load, 35 A - 100 A) Dynamic VID Testing
The VTT tool provides for VID stepping based on the Intel Requirements. Select the Dynamic VID option. Before enabling the test set the lowest VID to 0.5 V or greater and set the highest VID to a value that is greater than
Figure 8. Dynamic VID Settling Time Rising (CH1: VID1, CH2: DAC, CH3:VCCP)
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NCP5392Q
DESIGN METHODOLOGY
Decoupling the VCC Pin on the IC Programming the Current Limit and the Oscillator Frequency
An RC input filter is required as shown in the VCC pin to minimize supply noise on the IC. The resistor should be sized such that it does not generate a large voltage drop between 5 V supply and the IC.
Understanding Soft-Start
The controller supports typical VR11 startup routines. Vcore voltage ramps to the 1.1 V boot voltage, with a pause to capture the VID code then resume ramping to target value based on internal slew rate limit. The initial ramp rate was set to be 0.8 mV/mS.
The demo board is set for an operating frequency of approximately 330 kHz. The ROSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Then calculate the individual RLIM1 and RLIM2 values for the divider. The series resistors RLIM1 and RLIM2 sink current from the ILIM pin to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the total resistance. The total resistance may be estimated by Equation 1. This equation is valid for the individual phase frequency in both three and four phase mode.
Rosc ^ 20947 FSW *1.1262 330
*1.1262
(eq. 1)
30.5 kW ^ 20947
60 50 40 30 20 10
Rosc-kohm
Figure 9. VR11.1 Startup
0 100
Calculation Real Freq-kHz 1000
Figure 11. ROSC vs. Frequency
The current limit function is based on the total sensed current of all phases multiplied by a controlled gain (Acssum*Adrp). DCR sensed inductor current is a function of the winding temperature. The best approach is to set the maximum current limit based on expected average maximum temperature of the inductor windings,
DCRTmax + DCR 25C(1 ) 0.00393 @ (Tmax * 25)) (eq. 2)
For multiphase controller, the ripple current can be calculated as,
Ipp + (Vin * N @ V out) @ Vout L @ F SW @ Vin
(eq. 3)
Therefore calculate the current limit voltage as below,
Figure 10. VR11.1 Biased Startup VLIMIT ^ A CSSUM @ A DRP @ DCR Tmax @ (I MIN_OCP @ ) 0.5 @ Ipp) VLIMIT ^ A CSSUM @ A DRP @ DCR Tmax @ I MIN_OCP @ ) 0.5 @ (Vin * N @ V out) @ V out L @ F SW @ V in
(eq. 4)
In Equation 4, ACSSUM and ADRP are the gain of current summing amplifier and droop amplifier.
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NCP5392Q
Acssum I1 I2 I3 I4 Ilim RISO1 + RSUM RT2 - + Adrp RNOR RISO2
+ -
OCP event
Figure 12. ACSSUM and ADRP
RISO1 and RISO2 are in series with RT2, the NTC temperature sense resistor placed near inductor. RSUM is the resistor connecting between pin VDFB and pin CSSUM. If PSI = 1, PSI function is off, the current limit follows the Equation 7; if PSI = 0, the power saving mode will be enabled, COEpsi is a coefficient for the current limiting related with power saving function (PSI), the current limit can be calculated from Equation 8. COEpsi value is one over the original phase count N. Refer to the PSI and phase shedding section for more details.
As introduced before, VLIMIT comes from a resistor divider connected to Rosc pin, thus,
VLIMIT + 2 V @ ACSSUM + *4 ADRP + * RLIM2 @ COEpsi RLIM1 ) RLIM2
(eq. 5)
RNOR @ (RISO1 ) RISO2 ) RT2) (eq. 6) (R NOR ) RISO1 ) RISO2 ) RT2) @ RSUM
Final Equations for the Current Limit Threshold
Final equations are described based on two conditions: normal mode and PSI mode.
ILIMIT(normal) ^
2V@R LIM2 R LIM1)R LIM2
4@
@(R )R )R T2) NOR ISO1 ISO2 (R )R )R )R T2)@R NOR ISO1 ISO2 SUM
R
@ DCR 25C(1 ) 0.00393 @ (Tinductor * 25)) @ COEpsi
* 0.5 @
(V in * N @ V out) @ V out L @ F SW @ V in
(eq. 7)
ILIMIT(PSI) ^
2V@R LIM2 R LIM1)R LIM2
4@
@(R )R )R T2) NOR ISO1 ISO2 (R )R )R )R T2)@R NOR ISO1 ISO2 SUM
R
@ DCR 25C(1 ) 0.00393 @ (Tinductor * 25))
* 0.5 @
(V in * V out) @ Vout L @ FSW @ Vin
(eq. 8)
N is the number of phases involved in the circuit. The inductors on the demo board have a DCR at 25C of 0.6 mW. Selecting the closest available values of 21.3 kW for RLIM1 and 9.28 kW for RLIM2 yields a nominal operating frequency of 330 kHz. Select RISO1 = 1 k, RISO2 = 1 k, RT2 = 10 K (25C), RNOR/RSUM = 2, (refer to application diagram). That results to an approximate current limit of 133 A at 100C for a four phase operation and 131 A at 25C. The total sensed current can be observed as a scaled voltage at the VDRP with a positive no-load offset of approximately 1.3 V.
Inductor Selection
Inductor Current Sensing Compensation
The NCP5392Q uses the inductor current sensing method. An RC filter is selected to cancel out the impedance from inductor and recover the current information through the inductor's DCR. This is done by matching the RC time constant of the sensing filter to the L/DCR time constant. The first cut approach is to use a 0.1 mF capacitor for C and then solve for R.
L Rsense(T) + 0.1 @ mF @ DCR 25C @ (1 ) 0.00393(T * 25))
(eq. 9)
When using inductor current sensing it is recommended that the inductor does not saturate by more than 10% at maximum load. The inductor also must not go into hard saturation before current limit trips. The demo board includes a four phase output filter using the T44-8 core from Micrometals with 3 turns and a DCR target of 0.6 mW @ 25C. Smaller DCR values can be used, however, current sharing accuracy and droop accuracy decrease as DCR decreases. Use the NCP5392Q design aide for regulation accuracy calculations for specific value of DCR.
Because the inductor value is a function of load and inductor temperature final selection of R is best done experimentally on the bench by monitoring the Vdroop pin and performing a step load test on the actual solution.
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NCP5392Q
Simple Average SPICE Model
A simple state average model shown in Figure 13 can be used to determine a stable solution and provide insight into the control system.
GAIN = 1 {-2/3*4} Voff + E1 + -- E GAIN = {6} L LBRD RBRD 2 DCR 1 1 2 {185e-9/4} {0.6E-3/4} 100p 0.75m CBulk {560e-6*6} ESRBulk {7e-3/6} 2 ESLBulk {3.5e-9/6} 1 RDAC CDAC 50 CFB1 680P RFB 1k Voff Voffset 1.3V 0 RFB1 69.8 12n
V3 12V 0
0 0 12
VRamp_min 1.3V
RSUM 1k RDFB 22p CDFB
Voff
R8 1k
2k
1E3 Vdrp
CCer {22e-6*18} ESRCer {1.5e-3/18} 0Aac 2 0Adc ESLCer {1.5e-9/18} 1
I1 = 50 I2 = 110 I1 TD = 100u TR = 50n TF = 50n Vout PW = 100u PER = 200u
C5 10.6p 0 CH R12 5.11k CF 1.8n R6
RF 1E3 2.2k
22p
0 VDAC DC = 1.2V AC = 0 TRAN = PULSE (0 0.05 400u 5u 5u 500u 1000u) 0 R11 1k R9 1k 10.6p Vdrp R10 2k C6 0 1E3 Voff IMON
Unity Gain BW=15MHz
C4 1k 10.6p 0
Figure 13. NCP5392Q Average SPICE Model Compensation and Output Filter Design
If the required output filter and switching frequency are significantly different, it's best to use the available PSPICE models to design the compensation and output filter from scratch. The design target for this demo board was 1.0 mW up to 2.0 MHz. The phase switching frequency is currently set to 330 kHz. It can easily be seen that the board impedance of 0.75 mW between the load and the bulk capacitance has a large effect on the output filter. In this case the six 560 mF bulk capacitors have an ESR of 7.0 mW. Thus the bulk ESR
plus the board impedance is 1.15 mW + 0.75 mW or 1.9 mW. The actual output filter impedance does not drop to 1.0 mW until the ceramic breaks in at over 375 kHz. The controller must provide some loop gain slightly less than one out to a frequency in excess 300 kHz. At frequencies below where the bulk capacitance ESR breaks with the bulk capacitance, the DC-DC converter must have sufficiently high gain to control the output impedance completely. Standard Type-3 compensation works well with the NCP5392Q.
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NCP5392Q
Zout Open Loop Zout Closed Loop Open Loop Gain with Current Loop Closed Voltage Loop Compensation Gain 80 60 40 20 0 dB -20 -40 -60 -80 -100 100 1000 10000 Frequency 100000 1000000 10000000 1mOhm
Figure 14. NCP5392Q Circuit Frequency Response
The goal is to compensate the system such that the resulting gain generates constant output impedance from DC up to the frequency where the ceramic takes over holding the impedance below 1.0 mW. See the example of the locations of the poles and zeros that were set to optimize the model above. By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter.
1 1 + (eq. 10) 2p @ CF @ RF 2p @ (RBRD ) ESR Bulk) @ C Bulk
(eq. 11) 1 1 + 2p @ CFB1 @ (RFB1 ) RFB) 2p @ CCer @ (RBRD ) ESR Bulk)
CH RFB1 CFB1 I Bias RFB Droop Amp + - RNOR 1.3 V RF CF - + + - PWM Comparator
RDRP RISO2 RT RISO1 RSUM
Error Amp
1.3 V
Gain = 4 - + CSSUM Amp RSx 1.3 V CSx + - Gain = 1
+ +
RFB should be set to provide optimal thermal compensation in conjunction with thermistor RT2, RISO1 and RISO2. With RFB set to 1.0 kW, RFB1 is usually set to 100 W for maximum phase boost, and the value of RF is typically set to 3.0 kW.
Droop Injection and Thermal Compensation
RL
Figure 15. Droop Injection and Thermal Compensation
The VDRP signal is generated by summing the sensed output currents for each phase. A droop amplifier is added to adjust the total gain to approximately eight. VDRP is externally summed into the feedback network by the resistor RDRP. This introduces an offset which is proportional to the output current thereby forcing a controlled, resistive output impedance.
RDRP determines the target output impedance by the basic equation:
R @ DCR @ A CSSUM @ A DRP Vout + Z out + FB (eq. 12) Iout R DRP RDRP + R FB @ DCR @ ACSSUM @ ADRP Zout
(eq. 13)
The value of the inductor's DCR is a function of temperature according to the Equation 14:
DCR (T) + DCR25C @ (1 ) 0.00393 @ (T * 25)) (eq. 14)
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NCP5392Q
Actual DCR increases by temperature, the system can be thermally compensated to cancel this effect to a great degree by adding an NTC in parallel with RNOR to reduce the droop gain as the temperature increases. The NTC device is nonlinear. Putting a resistor in series with the NTC helps make the device appear more linear with
Zout(T) +
temperature. The series resistor is split and inserted on both sides of the NTC to reduce noise injection into the feedback loop. The recommended total value for RISO1 plus RISO2 is approximately 1.0 kW. The output impedance varies with inductor temperature by the equation:
(eq. 15)
R FB @ DCR 25C @ (1 ) 0.00393 @ (T * 25)) @ ACSSUM @ ADRP RDRP
R @(R )R )R T2) NOR ISO1 ISO2 )R )R )R T2)@R NOR ISO1 ISO2 SUM
By including the NTC RT2 and the series isolation resistors the new equation becomes:
Zout(T) + R FB @ DCR 25C @ (1 ) 0.00393 @ (T * 25)) @ ACSSUM @ (R RDRP
(eq. 16)
The typical equation of an NTC is based on a curve fit Equation 17
RT2(T) + RT2 25C @ e
b 1 1 * 273)T 298
Acssum I1 I2 I3 I4 Ilim RISO1 + RSUM
Adrp RNOR RT2 - + RISO2
(eq. 17)
The demo board use a 10 kW NTC with a b value of 3740. Figure 16 shows the comparison of the compensated output impedance and uncompensated output impedance varying with temperature.
0.0013 0.0012 0.0011 Ohm 0.001 0.0009 0.0008 0.0007 Zout Zout(uncomp)
+ -
OCP event
Imon + - Gain = 2
Figure 17. IMON Circuit
1.05 0.84 Vimon-V 25 45 Celsius 65 85 105 0.63 0.42 0.21 0 Vimon vs. Iout
0.0006
Figure 16. Zout vs. Temperature IMON for Current Monitor
Since VDRP signal reflects the current information of all phases. It can be fed into the IMON amplifier for current monitoring as shown in Figure 17. IMON amplifier has a fixed gain of 2 with an offset when VDRP is equal to 1.3 V, the internal floating reference voltage. The IMON amplifier will be saturated at an maximum output of 1.09 V therefore the total gain of current should be carefully considered to make the maximum load current indicated by the IMON output. Figure 18 shows a typical of the relation between IMON output and the load current.
0
10
20
30
40
Figure 18. IMON Output vs. Output Current Power Saving Indicator (PSI) and Phase Shedding
50 60 Iout-A
70
80
90 100
VR11.1 requires the processor to provide an output signal to the VR controller to indicate when the processor is in a low power state. NCP5392Q use the status of PSI pin to decide if there is a need to change its operating state to maximize efficiency at light loads. When PSI = 0, the PSI function will be enabled, and VR system will be running at a single phase power saving mode. The PSI signal will de-assert 1 ms prior to moving to a normal power state.
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NCP5392Q
When system switches on PSI function, a phase shedding will be presented. Only one is active in the emulation mode while other phases are shed. Figure 19 indicates a PSI-on transition from a 3-phase mode to a single phase mode. While staying stable in PSI mode, the PWM signal of phase 1 will vary from a low-state level to high level while other phases all go to mid-state level (1.5 V typical). Vice verse, when PSI signal goes high, the system will go back to the original phase mode such as shown in Figure 20.
Auto-PSI Function:
In Auto-PSI mode (APSI_EN=1, PSI=1), the device will monitor VID lines for transition into/out-of Low Power States. Figures 21 and 22 describe the Auto-PSI function during VID transitions.
Figure 21. 10 A Load, VID Down, into PSI, CH1: PWM1, CH2: PWM2, CH3: PWM3, CH4: VOUT
Figure 19. PSI turns on, CH1: PWM1, CH2: PWM2, CH3: PWM3, CH4: PSI
Figure 22. 10 A Load, VID Up, Out of PSI, CH1: PWM1, CH2: PWM2, CH3: PWM3, CH4: VOUT
Figure 20. PSI turns off, CH1: PWM1, CH2: PWM2, CH3: PWM3, CH4: PSI
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NCP5392Q
OVP Improved Performance Gate Driver and MOSFET Selection
The overvoltage protection threshold is not adjustable. OVP protection is enabled as soon as soft-start begins and is disabled when part is disabled. When OVP is tripped, the controller commands all four gate drivers to enable their low side MOSFETs and VR_RDY transitions low. In order to recover from an OVP condition, VCC must fall below the UVLO threshold. See the state diagram for further details. The OVP circuit monitors the output of DIFFOUT. If the DIFFOUT signal reaches 180 mV (typical) above the nominal 1.3 V offset the OVP will trip and VRRDY will be pulled low, after eight consecutive OVP events are detected, all PWMs will be latched. The DIFFOUT signal is the difference between the output voltage and the DAC voltage (minus 19 mV if in VR11.1 modes) plus the 1.3 V internal offset. This results in the OVP tracking on the DAC voltage even during a dynamic change in the VID setting during operation.
ON Semiconductor provides the NCP5359 as a companion gate driver IC. The NCP5359 driver is optimized to work with a range of MOSFETs commonly used in CPU applications. The NCP5359 provides special functionality including power saving mode operation and is required for high performance dynamic VID operation. Contact your local ON Semiconductor applications engineer for MOSFET recommendations.
Board Stackup and Board Layout
Close attention should be paid to the routing of the sense traces and control lines that propagate away from the controller IC. Routing should follow the demo board example. For further information or layout review contact ON Semiconductor.
Figure 23. VR11.1, 1.6 V OVP Event
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NCP5392Q
SYSTEM TIMING DIAGRAM
12 V (Gate Driver) UVLO 5 V (Controller) UVLO EN VID Valid VID 3.5 ms
DRVON 1.5 ms
1 ms min
500 ms VSP-VSN 500 ms VR_RDY
Figure 24. Normal Startup
UVLO UVLO 5 V (Controller) POR
12 V (Gate Driver)
EN
3.5 ms
DRVON VID Valid VID 1 ms min 1.5 ms 1 ms 500 ms
VSP-VSN
500 ms VR_RDY
Figure 25. Driver UVLO Limited Startup
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NCP5392Q
1 Diffout ~ 1.3 V 185 mV 2 3 4 5 6 7 8
VR_RDY
DRVON = High
1 VSP = VID - 19 mV 185 mV
2
3
4
5
6
7
8
Figure 26. OVP Shutdown
Ilimit + 1.3
VDRP
VR_RDY
DRVON
Figure 27. Non-PSI Current Limit
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NCP5392Q
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P CASE 488AR-01 ISSUE A
D
PIN ONE LOCATION
AB
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 4.00 4.20 6.00 BSC 4.00 4.20 0.50 BSC 0.30 0.50 0.20 ---
2X
0.15 C
2X
0.15 C 0.10 C
40X
0.08 C
40X 10 EXPOSED PAD
L
b 0.10 C A B
40X
0.05 C
The products described herein (NCP5392Q), is covered by one or more of the following U.S. patent; US07057381. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative
EEEE EEEE EEEE EEEE
D2
11 1 40
E
TOP VIEW (A3) A
SIDE VIEW A1 C
20 21 SEATING PLANE
SOLDERING FOOTPRINT*
6.30 4.20 0.65 1
40X
40X
K
E2 4.20 6.30
30 31
e BOTTOM VIEW
36X 40X
0.30
0.50 PITCH
DIMENSIONS: MILLIMETERS
36X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5392Q/D

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